As chip design approaches maximum density, new materials and processes are necessary to optimize performance and functionality while minimizing feature sizes.
Current Research:
- Computational design of materials for low-resistance interconnects needed for further downscaling chips and for future computing technologies, e.g., spintronics and quantum computers, using simulations of electron transport and quantum dynamics
- Materials synthesis and device fabrication/tests focusing on spintronics, neuromorphic computing, optoelectronics, and ferroelectric logic/memory
- Epitaxial layer growth and in situ transport measurements employed to study and discover new materials for future interconnects which yield high conductivity at small (<10 nm) dimensions
- Interfacial engineering (e.g., metal-dielectric, metal-semiconductor) for tailoring multiple properties (electronic and thermal transport, adhesion, chemical stability)
- Thermoelectric materials and interfaces for thermal management
- Bacterial cellulose and cellulose nanocrystals that provide ordered 2D and 3D matrices to host inorganic nanoparticles, metal ions, carbon nanotubes, graphene, and more to give electro-conducting composites
